OMAP5910JZZG2 Datasheet, PDF (93/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Functional Overview
Table 3--46. Traffic Controller Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS ACCESS
WIDTH TYPE
RESET
VALUE
FFFE:CC00 IMIF_PRIO
TC IMIF Priority Register
32
RW
0000 0000h
FFFE:CC04 EMIFS_PRIO_REG
TC EMIFS Priority Register
32
RW
0000 0000h
FFFE:CC08 EMIFF_PRIO_REG
FFFE:CC0C EMIFS_CONFIG_REG
TC EMIFF Priority Register
TC EMIFS Configuration Register
32
RW
0000 0000h
32
RW
y00z0b^†
FFFE:CC10 EMIFS_CS0_CONFIG
TC EMIFS CS0 Configuration Register
32
RW
0010 FFFBh
FFFE:CC14 EMIFS_CS1_CONFIG
TC EMIFS CS1 Configuration Register
32
RW
0010 FFFBh
FFFE:CC18 EMIFS_CS2_CONFIG
TC EMIFS CS2 Configuration Register
32
RW
0010 FFFBh
FFFE:CC1C EMIFS_CS3_CONFIG
TC EMIFS CS3 Configuration Register
32
RW
0010 FFFBh
FFFE:CC20 EMIFF_SDRAM_CONFIG
TC EMIFF SDRAM Configuration Register
32
RW
0061 8800h
FFFE:CC24 EMIFF_MRS
TC EMIFF SDRAM MRS Register
32
RW
0000 0037h
FFFE:CC28 TIMEOUT1
TC Timeout 1 Register
32
RW
0000 0000h
FFFE:CC2C TIMEOUT2
TC Timeout 2 Register
32
RW
0000 0000h
FFFE:CC30 TIMEOUT3
TC Timeout 3 Register
32
RW
0000 0000h
FFFE:CC34 ENDIANISM
TC Endianism Register
32
RW
0000 0000h
FFFE:CC38
Reserved
32
RW
0000 0000h
FFFE:CC3C EMIFF_SDRAM_CONFIG_2
TC EMIFF SDRAM Configuration Register 2
32
RW
0000 0003h
FFFE:CC40 EMIFS_CFG_DYN_WAIT
TC EMIFS Wait-State Configuration Register
32
RW
0000 0000h
† _{The value of y is dependent upon the state of the FLASH.RDY pin and the value of z is dependent upon the state of the MPU_BOOT pin upon}
power-on reset.
Table 3--47. MPU Clock/Reset/Power Mode Control Registers
BYTE
ADDRESS
FFFE:CE00
FFFE:CE04
FFFE:CE08
FFFE:CE0C
FFFE:CE10
FFFE:CE14
FFFE:CE18
REGISTER NAME
ARM_CKCTL
ARM_IDLECT1
ARM_IDLECT2
ARM_EWUPCT
ARM_RSTCT1
ARM_RSTCT2
ARM_SYSST
DESCRIPTION
MPU Clock Control Register
MPU Idle Control 1 Register
MPU Idle Control 2 Register
MPU External Wakeup Control Register
MPU Reset Control 1 Register
MPU Reset Control 2 Register
MPU System Status Register
ACCESS ACCESS
WIDTH TYPE
32
RW
32
RW
32
RW
32
RW
32
RW
32
RW
32
RW
RESET
VALUE
3000h
0400h
0100h
003Fh
0000h
0000h
0038h
BYTE
ADDRESS
FFFE:CF00
REGISTER NAME
DPLL1_CTL_REG
Table 3--48. DPLL1 Register
DESCRIPTION
DPLL1 Control Register
ACCESS ACCESS
WIDTH TYPE
32
RW
RESET
VALUE
0000 2002h
August 2002 -- Revised August 2004
SPRS197D
93