OMAP5910JZZG2 Datasheet, PDF (27/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Introduction
Table 2--3. Terminal Characteristics and Multiplexing (Continued)
GZG GDY
BALL BALL
SIGNAL NAME
TYPE^†
MUX CTRL
SETTING^‡
DESELECTED
INPUT STATE
PU/
PD^§
BUFFER
STRENGTH
OTHER^¶
RESET
STATE^#
H18 F16 MCBSP1.DX
O
reg4[17:15] = 000
NA
4 mA
J, B, G1
0
MCBSP1.FSX
I/O/Z
reg4[17:15] = 001
0
H20 G16 MCBSP1.DR
I
NA
NA
PD20
B,J
input
H19 G13 CAM.EXCLK
O
reg4[23:21] = 000
NA
8 mA
J, A, G1
0
ETM.SYNC
O
reg4[23:21] = 001
NA
UWIRE.SDO
O
reg4[23:21] = 010
NA
J15
H15 CAM.LCLK
I
reg4[26:24] = 000
0
8 mA
B, J
input
ETM.CLK
O
reg4[26:24] = 001
NA
UWIRE.SCLK
O
reg4[26:24] = 010
NA
J18
G14 CAM.D[7]
I
reg4[29:27] = 000
NA
8 mA
B, J
input
ETM.D[7]
O
reg4[29:27] = 001
NA
UWIRE.CS0
O
reg4[29:27] = 010
NA
J19
G12 CAM.D[6]
I
reg5[2:0] = 000
NA
8 mA
B, J
input
ETM.D[6]
O
reg5[2:0] = 001
NA
UWIRE.CS3
O
reg5[2:0] = 010
NA
J14
H16 CAM.D[5]
I
reg5[5:3] = 000
NA
8 mA
B, J
input
ETM.D[5]
O
reg5[5:3] = 001
NA
UWIRE.SDI
I
reg5[5:3] = 010
NA
PD20
K18
J15 CAM.D[4]
I
reg5[8:6] = 000
NA
8 mA
B, J
input
ETM.D[4]
O
reg5[8:6] = 001
NA
UART3.TX
O
reg5[8:6] = 010
NA
K19 G17 CAM.D[3]
I
reg5[11:9] = 000
NA
8 mA
B, J
input
ETM.D[3]
O
reg5[11:9] = 001
NA
UART3.RX
I
reg5[11:9] = 010
NA
PD20
K15 H17 CAM.D[2]
I
reg5[14:12] = 000
NA
8 mA
B, J
input
ETM.D[2]
O
reg5[14:12] = 001
NA
UART3.CTS
I
reg5[14:12] = 010
NA
PD20
K14 H14 CAM.D[1]
I
reg5[17:15] = 000
NA
8 mA
B, J
input
ETM.D[1]
O
reg5[17:15] = 001
NA
UART3.RTS
O
reg5[17:15] = 010
NA
L19
J16 CAM.D[0]
I
reg5[20:18] = 000
NA
8 mA
B, J
input
ETM.D[0]
O
reg5[20:18] = 001
NA
MPUIO12
I/O/Z
reg5[20:18] = 010
NA
L18
J17 CAM.VS
I
reg5[23:21] = 000
NA
8 mA
B, J
input
ETM.PSTAT[2]
O
reg5[23:21] = 001
NA
L15
K15 CAM.HS
I
reg5[26:24] = 000
NA
8 mA
B, J
input
ETM.PSTAT[1]
O
reg5[26:24] = 001
NA
UART2.CTS
I
reg5[26:24] = 010
NA
PD20
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x}
§ _{PD20 = 20-μA internal pulldown, PD100 = 100-μA pulldown, PU20 = 20-μA internal pullup, PU100 = 100-μA internal pullup}
¶ _{A = Standard LVCMOS input/output}
G1 = Terminal may be gated by BFAIL
B = Fail-safe LVCMOS input/output
G2 = Terminal may be gated by GPIO9 and MPUIO3
C = USB transceiver input/output
D = I²C input/output buffers
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
E = Fail-safe LVCMOS input and Standard LVCMOS output J = Boundary-scannable terminal
F = analog oscillator terminals
# _{Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low}
|| _{UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.}
SUPPLY
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD8
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD1
DV_DD1
August 2002 -- Revised August 2004
SPRS197D
27