OMAP5910JZZG2 Datasheet, PDF (110/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Functional Overview
Table 3--69. UART2 Registers
DSP WORD MPU BYTE
ADDRESS ADDRESS
0x00 8400h
0x00 8400h
0x00 8400h
0x00 8401h
0x00 8401h
FFFB:0800
FFFB:0800
FFFB:0800
FFFB:0804
FFFB:0804
MPU BYTE
ADDRESS
(VIA MPUI)
E101:0800
E101:0800
E101:0800
E101:0802
E101:0802
REGISTER
NAME
UART2_RHR^†
UART2_THR^†
UART2_DLL^‡§
UART2_IER^†
UART2_DLH^‡§
DESCRIPTION
UART2 Receive Holding Register
UART2 Transmit Holding Register
UART2 Divisor Latch Low Register
UART2 Interrupt Enable Register
UART2 Divisor Latch High Register
0x00 8402h FFFB:0808
0x00 8402h FFFB:0808
0x00 8402h FFFB:0808
E101:0804
E101:0804
E101:0804
UART2_IIR^†‡
UART2_FCR^{†‡¶}
UART2_EFR^§
UART2 Interrupt Identification
Register
UART2 FIFO Control Register
UART2 Enhanced Feature Register
0x00 8403h
0x00 8404h
0x00 8404h
0x00 8405h
0x00 8405h
0x00 8406h
FFFB:080C
FFFB:0810
FFFB:0810
FFFB:0814
FFFB:0814
FFFB:0818
E101:0806
E101:0808
E101:0808
E101:080A
E101:080A
E101:080C
UART2_LCR
UART2_MCR^{†‡¶}
UART2_XON1^§
UART2_LSR^†‡
UART2_XON2^§
UART2_MSR^†‡
UART2 Line Control Register
UART2 Modem Control Register
UART2 XON1 Register
UART2 Mode Register
UART2 XON2 Register
UART2 Modem Status Register
0x00 8406h FFFB:0818 E101:080C UART2_TCR^#
UART2 Transmission Control
Register
0x00 8406h
0x00 8407h
0x00 8407h
0x00 8407h
FFFB:0818
FFFB:081C
FFFB:081C
FFFB:081C
E101:080C
E101:080E
E101:080E
E101:080E
UART2_XOFF1^§
UART2_SPR^†‡
UART2_TLR^#
UART2_XOFF2^§
UART2 XOFF1 Register
UART2 Scratchpad Register
UART2 Trigger Level Register
UART2 XOFF2 Register
0x00 8408h FFFB:0820 E101:0810 UART2_MDR1 UART2 Mode Definition 1 Register
0x00 8409 -- FFFB:0824 --
0x00840Dh FFFB:0834
0x00 840Eh FFFB:0838 E101:081C
Reserved
UART2_UASR^ठUART2 Autobauding Status Register
0x00 840Fh FFFB:083C
Reserved
0x00 8410h FFFB:0840 E101:0820 UART2_SCR
UART2 Supplementary Control
Register
0x00 8411h FFFB:0844 E101:0822 UART2_SSR
UART2 Supplementary Status
Register
0x00 8412h FFFB:0848
Reserved
0x00 8413h FFFB:084C E101:0826
UART2_OSC_
12M_SELV^†
UART2 12-/13-MHz Oscillator Select
Register
0x00 8414h FFFB:0850 E101:0828 UART2_MVR UART2 Module Version Register
† _{Register is accessible when LCR[7] = 0 (normal operating mode)}
‡ _{Register is accessible when LCR[7] = 1 and LCR[7:0] ¸ 0BFh}
§ _{Register is accessible when LCR[7] = 0BFh}
¶ _{Register is write accessible when EFR[4] = 1}
# _{Register is accessible when EFR[4] = 1 and MCR[6] = 1}
ACCESS ACCESS
WIDTH TYPE
8
R
8
W
8
RW
8
RW
8
RW
8
R
8
W
8
RW
8
RW
8
RW
8
RW
8
R
8
RW
8
R
8
RW
8
RW
8
RW
8
RW
8
RW
8
RW
8
R
8
RW
8
R
8
W
8
R
RESET
VALUE
Undefined
Undefined
00h
00h
00h
01h
00h
00h
00h
00h
00h
60h
00h
Undefined
0Fh
00h
00h
00h
00h
07h
00h
00h
00h
00h
--
110 SPRS197D
August 2002 -- Revised August 2004