OMAP5910JZZG2 Datasheet, PDF (148/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Electrical Specifications
Table 5--22. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)^†‡
MASTER
SLAVE
NO.
MIN
UNIT
MIN MAX
MIN MAX
M58 t_su(DRV-CKXL)
Setup time, MCBSPx.DR valid before MCBSPx.CLKX low
15
2 -- 6P
ns
M59 t_h(CKXL-DRV)
Hold time, MCBSPx.DR valid after MCBSPx.CLKX low
2
6 + 6P
ns
M60 t_su(FXL-CKXL)
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX low
McBSP1
McBSP2
McBSP3
21
5
ns
10
M61 t_c(CKX)
Cycle time, MCBSPx.CLKX
2P
16P
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.}
Table 5--23. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)^†‡
NO.
PARAMETER
MASTER^§
MIN MAX
SLAVE
UNIT
MIN
MAX
M53 t_h(CKXH-FXL)
Hold time, MCBSPx.FSX low after MCBSPx.CLKX
high^¶
0.45D
0.55D
ns
M54 t_d(FXL-CKXL)
Delay time, MCBSPx.FSX low to MCBSPx.CLKX low^# 0.45T 0.55T
ns
M55 t_d(CKXH-DXV)
Delay time, MCBSPx.CLKX high to MCBSPx.DX valid
--1
7 3P + 2 5P + 18 ns
M57 t_d(FXL-DXV)
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
C + 20
4P + 18 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input}
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master}
clock (MCBSPx.CLKX).
LSB
M60
MSB
M61
MCBSPx.CLKX
MCBSPx.FSX
MCBSPx.DX
MCBSPx.DR
Bit 0
Bit 0
M53
M54
M57
M58
Bit(n-1)
Bit(n-1)
M55
(n-2)
M59
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5--23. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
148 SPRS197D
August 2002 -- Revised August 2004