OMAP5910JZZG2 Datasheet, PDF (146/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Electrical Specifications
Table 5--18. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)^†‡
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M39 t_su(DRV-CKXH) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high
15
2 -- 6P
ns
M40 t_h(CKXH-DRV)
Hold time, MCBSPx.DR valid after MCBSPx.CLKX high
2
6 +6P
ns
M41 t_su(FXL-CKXH)
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX high
McBSP1
McBSP2
McBSP3
21
5
ns
10
M42 t_c(CKX)
Cycle time, MCBSPx.CLKX
2P
16P
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.}
Table 5--19. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)^†‡
MASTER^§
SLAVE
NO.
PARAMETER
UNIT
MIN MAX
MIN
MAX
M34 t_h(CKXL-FXL)
Hold time, MCBSPx.FSX low after MCBSPx.CLKX low^¶ 0.45C 0.55C
ns
M35 t_d(FXL-CKXH)
Delay time, MCBSPx.FSX low to MCBSPx.CLKX high^# 0.45T 0.55T
ns
M36 t_d(CKXL-DXV)
Delay time, MCBSPx.CLKX low to MCBSPx.DX valid
--1
7 3P + 2 5P + 18 ns
M38 t_d(FXL-DXV)
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
D +20
4P + 18 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input}
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master}
clock (MCBSPx.CLKX).
MCBSPx.CLKX
MCBSPx.FSX
MCBSPx.DX
MCBSPx.DR
LSB
M34
Bit 0
Bit 0
M41
M35
M38
M39
MSB
M42
Bit(n-1)
Bit(n-1)
M36
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5--21. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
146 SPRS197D
August 2002 -- Revised August 2004