OMAP5910JZZG2 Datasheet, PDF (112/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Functional Overview
Table 3--70. UART3/IrDA Registers (Continued)
DSP WORD MPU BYTE
ADDRESS ADDRESS
MPU BYTE
ADDRESS
(VIA MPUI)
REGISTER
NAME
DESCRIPTION
0x00 CC0Fh FFFB:983C E101:981E UART3_DIV16^ठUART3 Divide 1.6 Register
0x00 CC10h FFFB:9840 E101:9820 UART3_SCR
UART3 Supplementary Control
Register
† _{Register is accessible when LCR[7] = 0 (normal operating mode)}
‡ _{Register is accessible when LCR[7] = 1 and LCR[7:0] ¸ 0BFh}
§ _{Register is accessible when LCR[7] = 0BFh}
¶ _{Register is write accessible when EFR[4] = 1}
# _{Register is accessible when EFR[4] = 1 and MCR[6] = 1}
ACCESS ACCESS
WIDTH TYPE
8
RW
8
RW
RESET
VALUE
00h
00h
Table 3--71. MPU/DSP Shared GPIO Registers
DSP WORD MPU BYTE
ADDRESS ADDRESS
0x00 F000h FFFC:E000
0x00 F002h FFFC:E004
REGISTER NAME
DATA_INPUT
DATA_OUTPUT
0x00 F004h FFFC:E008 DIRECTION_CONTROL
0x00 F006h FFFC:E00C
0x00 F008h
0x00 F00Ah
0x00 F00Ch
FFFC:E010
FFFC:E014
FFFC:E018
INTERRUPT_CONTROL
INTERRUPT_MASK
INTERRUPT_STATUS
PIN_CONTROL
DESCRIPTION
Data Input Register
Data Output Register
Direction Control
Register
Interrupt Control
Register
Interrupt Mask Register
Interrupt Status Register
Pin Control Register
ACCESS MPU
DSP
WIDTH ACCESS ACCESS
16
R
R
16
RW
RW
16
RW
RW
16
RW
RW
16
RW
RW
16
RW
RW
16
RW
R
RESET
VALUE
0000h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
FFFFh
DSP WORD
ADDRESS
0x00 F800h
0x00 F802h
0x00 F804h
0x00 F806h
0x00 F808h
0x00 F80Ah
0x00 F80Ch
0x00 F80Eh
0x00 F810h
0x00 F812h
0x00 F814h
0x00 F816h
MPU BYTE
ADDRESS
FFFC:F000
FFFC:F004
FFFC:F008
FFFC:F00C
FFFC:F010
FFFC:F014
FFFC:F018
FFFC:F01C
FFFC:F020
FFFC:F024
FFFC:F028
FFFC:F02C
Table 3--72. MPU/DSP Shared Mailbox Registers
REGISTER NAME
DESCRIPTION
MPU
DSP
ACCESS
WIDTH ^{ACCESS ACCESS}
TYPE
TYPE
ARM2DSP1
MPU to DSP 1 Data Register
16
RW
R
ARM2DSP1B
MPU to DSP 1 Command Register
16
RW
R
DSP2ARM1
DSP to MPU 1 Data Register
16
R
RW
DSP2ARM1B
DSP to MPU 1 Command Register
16
R
RW
DSP2ARM2
DSP to MPU 2 Data Register
16
R
RW
DSP2ARM2B
DSP to MPU 2 Command Register
16
R
RW
ARM2DSP1_FLAG MPU to DSP 1 Flag Register
16
R
R
DSP2ARM1_FLAG DSP to MPU 1 Flag Register
16
R
R
DSP2ARM2_FLAG DSP to MPU 2 Flag Register
16
R
R
ARM2DSP2
MPU to DSP 2 Data Register
16
RW
R
ARM2DSP2B
MPU to DSP 2 Command Register
16
RW
R
ARM2DSP2_FLAG MPU to DSP 2 Flag Register
16
R
R
RESET
VALUE
0000h
0000h
0000h
0000h
0000h
0000h
undef
undef
undef
0000h
0000h
undef
112 SPRS197D
August 2002 -- Revised August 2004