OMAP5910JZZG2 Datasheet, PDF (133/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Electrical Specifications
FLASH.CLK^†
(internal)
FLASH.CSx
FLASH.BE[1:0]
FLASH.A[24:1]
FLASH.D[15:0]
FLASH.ADV
FLASH.OE
M cycles^‡
N cycles^‡
F1
F1
F2
F3
Valid
F4
F5
A1
F6
F7
F6
F7
D1 lower
D1 upper
F8
F8
F9
F9
FLASH.WE
† _{FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to}
express relative timings.
‡ _{Number of cycles is configurable via EMIFS setup registers.}
Figure 5--8. Asynchronous 32-Bit Read
August 2002 -- Revised August 2004
SPRS197D 133