OMAP5910JZZG2 Datasheet, PDF (38/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Introduction
Table 2--4. Signal Description (Continued)
SIGNAL
GZG GDY
BALL BALL
DESCRIPTION
Multichannel Buffered Serial Ports (McBSPs) (Continued)
TYPE^†
MCBSP1.DX
MCBSP2.DX
MCBSP3.DX
H18, F16, McBSP transmit data. Serial transmit data output. DX is present on all McBSPs.
O
H15 F17
AA5, R5,
P10 R6
P14, U13,
W21 P16
MCBSP2.CLKR
V7
T5
McBSP2 receive clock. Serial shift clock reference for the receiver. CLKR is only
I/O/Z
present on McBSP2.
MCBSP2.FSR
W6 P6
McBSP2 receive frame sync. Frame synchronization for the receiver. FSR is only
present on McBSP2.
I/O/Z
MCBSP1.DR
MCBSP2.DR
MCBSP3.DR
H20 G16 McBSP receive data. Serial receive data input. DR is present on all McBSPs.
I
P10, R6,
AA5 R5
AA17, R12,
U18 P17
Camera Interface
CAM.EXCLK
H19 G13 Camera interface external clock. Output clock used to provide a timing reference
O
to a camera sensor.
CAM.LCLK
J15 H15 Camera interface line clock. Input clock to provide external timing reference from
I
camera sensor logic.
CAM.VS
L18 J17 Camera interface vertical sync. Vertical synchronization input from external
I
camera sensor.
CAM.HS
L15 K15 Camera interface horizontal sync. Horizontal synchronization input from external
I
camera sensor.
CAM.D[7:0]
J18, G14, Camera interface data. Data input bus to receive image data from an external
I
J19, G12, camera sensor.
J14, H16,
K18, J15,
K19, G17,
K15, H17,
K14, H14,
L19 J16
CAM.RSTZ
M19 J14 Camera interface reset. Reset output used to reset or Initialize external camera
O
sensor logic.
ETM9 Trace Macro Interface
ETM.CLK
J15 H15 ETM9 Trace Clock. Clock output for standard ETM9 test/debug equipment.
O
ETM.SYNC
H19 G13 ETM9 Trace Synchronization. Trace Sync output for standard ETM9 test/debug
O
equipment.
ETM.D[7:0]
J18, G14, ETM9 Trace Packet data. Trace Packet outputs for standard ETM9 test/debug
O
J19, G12, equipment.
J14, H16,
K18, J15,
K19, G17,
K15, H17,
K14, H14,
L19 J16
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain}
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§ _{See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.}
38 SPRS197D
August 2002 -- Revised August 2004