OMAP5910JZZG2 Datasheet, PDF (46/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Introduction
Table 2--4. Signal Description (Continued)
SIGNAL
GZG GDY
BALL BALL
DESCRIPTION
TYPE^†
Power Supplies (Continued)
CV_DDA‡
Y21 R15 Analog supply voltage. Supplies power to ULPD DPLL which provides an internal power
clock to the USB peripherals. NOTE: The voltage to this supply pin should be kept
as clean as possible to maximize performance.
DV_DD1
A15,
A19,
E21,
L21,
U21,
AA11,
Y16
C12,
A14,
E14,
H13,
N16,
P9,
T12
I/O Supply Voltage 1. Supplies power to the majority of peripheral I/O buffers.
DV_DD1 may be connected in common with the other DV_DD supplies if the same
operating voltage is desired.
power
DV_DD2
AA2 U3
I/O Supply Voltage 2. Supplies power to the internal USB transceiver buffers.
DV_DD2 may optionally be used for USB connect and disconnect detection by
connecting DV_DD2 to the power from the USB bus in the system. DV_DD2 may be
connected in common with the other DV_DD supplies if the same operating voltage
is desired.
power
DV_DD3
Y7 N7 I/O Supply Voltage 3. Supplies power to the MCSI2 and McBSP2 peripheral I/O
power
buffers as well as GPIO[9:8] I/O buffers. The DV_DD3 supply may operate within a
high-voltage or low-voltage range (see Section 5.2 for operating conditions).
DV_DD3 may be connected in common with the other DV_DD supplies if the same
operating voltage is desired.
DV_DD4
A1, D3,
A5, D5,
A7, A5,
B10, D8,
B12 E10
I/O Supply Voltage 4. Supplies power to the SDRAM interface I/O buffers. The
DV_DD4 supply may operate within a high-voltage or low-voltage range (see
Section 5.2 for operating conditions). DV_DD4 may be connected in common with
the other DV_DD supplies if the same operating voltage is desired.
power
DV_DD5
C2, H7, I/O Supply Voltage 5. Supplies power to the FLASH interface I/O buffers. The
E1, D1, DV_DD5 supply may operate within a high-voltage or low-voltage range (see
H2, F1, Section 5.2 for operating conditions). DV_DD5 may be connected in common with
L1, K6, the other DV_DD supplies if the same operating voltage is desired.
P3, L2,
R1, L3,
V2 U1
power
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain}
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§ _{See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.}
46 SPRS197D
August 2002 -- Revised August 2004