OMAP5910JZZG2 Datasheet, PDF (71/171 Pages) Texas Instruments – This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes

Dedicated CV_DD for
ULPD DPLL
OMAP5910
ULPD DPLL
(for USB)
OMAP DPLL
Functional Overview
Dedicated CV_DD for
USB DPLL
V_SS^‡w
CV_DDA
CV_DD4
CV_DDx
Common CV_DD for
Rest of Chip
C = 10 μF
V_DD
R = 10 Ω
Voltage
RegulatorW
† _{This circuit is provided only as an example. Specific board layout implementation must minimize noise on the OMAP5910 voltage supply pins.}
‡ _{Except where stated otherwise in this document, all VSS pins on the OMAP5910 are common and must be connected directly to a common}
ground; however, the discrete capacitor in the RC filter circuit should be placed as close as possible to the V_SS (GZG balls AA1/Y3 or GDY balls
E13/K9).
§ _{For special consideration with respect to the connection of VSS (GZG ball V12 or GDY ball F6), refer to Section 5.6.1, 32-kHz Oscillator and Input}
Clock.
¶ _{The voltage regulator must be selected to provide a voltage source with minimal low frequency noise.}
Figure 3--6. External RC Circuit for DPLL CV_DD Noise Isolation^†
3.15 MPU Register Descriptions
The following tables describe the MPU registers including register addresses, descriptions, required access
widths, access types (R = read, W = write, RW = read/write) and reset values. These tables are organized
by function with like peripherals or functions together and are therefore not necessarily in the order of
ascending register addresses.
NOTE: All accesses to these registers must be of the data access widths indicated to avoid
a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never
be accessed.
August 2002 -- Revised August 2004
SPRS197D
71