LMF100_15 Datasheet, PDF (9/40 Pages) Texas Instruments – LMF100 Dual High-Performance Switched Capacitor Filters

www.ti.com
Logic Input Characteristics (continued)
All limits apply to T_A = T_J = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN Logical “1”
V⁺ = +2.5 V, V^− = −2.5 V,
Tested Limit⁽¹⁾
Design Limit⁽²⁾
CMOS Clock
Input Voltage
MAX Logical “0” V_LSh = 0 V
MIN Logical “1” V⁺ = +5 V, V^− = 0 V,
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
MAX Logical “0” V_LSh = +2.5 V
Tested Limit⁽¹⁾
Design Limit⁽²⁾
TTL Clock
Input Voltage
MIN Logical “1” V⁺ = +5 V, V^− = 0 V,
MAX Logical “0” V_LSh = 0 V, V_D+ = 0 V
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
LMF100CCN
MIN TYP MAX
1.5
1.5
−1.5
−1.5
4
4
1
1
2
2
0.8
0.8
LMF100CIWM
UNIT
MIN
TYP MAX
1.5 V
−1.5 V
4V
1V
2V
0.8 V
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: LMF100
Submit Documentation Feedback
9