LMF100_15 Datasheet, PDF (25/40 Pages) Texas Instruments – LMF100 Dual High-Performance Switched Capacitor Filters

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LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
Typical Application (continued)
9.2.1 Design Requirements
In order to design a filter using the LMF100, we must define the necessary values of three parameters for each
second-order section: f₀, the filter section’s center frequency; H₀, the passband gain; and the filter’s Q. These are
determined by the characteristics required of the filter being designed.
As an example, assume that a system requires a fourth-order Chebyshev lowpass filter with 1-dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order
sections of an LMF100. Many filter design texts (and TI Switched Capacitor Filter Handbook) include tables that
list the characteristics (_f0 and Q) of each of the second-order filter sections needed to synthesize a given higher-
order filter. For the Chebyshev filter defined above, such a table yields the following characteristics:
f_0A = 529 Hz — — Q_A = 0.785
f_0B = 993 Hz — — Q_B = 3.559
For unity gain at DC, we also specify:
H_0A = 1
H_0B = 1
The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100, and a 100-kHz clock signal
is available. The required center frequencies for the two second-order sections will not be obtainable with clock-
f_CLK
to-center-frequency ratios of 50 or 100. It will be necessary to adjust ^f0 externally. From Table 1, we see that
Mode 3 can be used to produce a lowpass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher
relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage
will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency.
For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a convenient value for the input resistance: R_1A = 20 k.
The absolute value of the passband gain H_OLPA is made equal to 1 by choosing R_4A such that: R_4A = −H_OLPAR_1A =
R_1A = 20 k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we
find R_2A by:
R_2A
= R_4A
f_{0 A} ²
(f_CLK / 100)²
= 2 ´10⁴ ´ ⁽⁵²⁹⁾²
(1000)²
= 5.6k
and
R_3A = Q_A R_2AR_4A = 0.785 5.6 ´10³ ´ 2 ´10⁴ = 8.3k
The resistors for the second section are found in a similar fashion:
R_1B = 20k
R_4B = R_1B = 20k
R_2B
= R_4B
f_0B2
(f_CLK / 100)²
=
20k
(993)²
(1000)²
= 19.7k
R_3B = Q_B R_2BR_4B = 3.559 1.97 ´10⁴ ´ 2 ´10⁴ = 70.6k
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