LMF100_15 Datasheet, PDF (32/40 Pages) Texas Instruments – LMF100 Dual High-Performance Switched Capacitor Filters

LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
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10 Power Supply Recommendations
The LMF100 can operate with a single-ended power supply as well as bipolar supplies. Refer to Figure 56
through Figure 58 for methods of generating V+/2 for single-supply operation. In this circumstance, pins VA+ and
VD+ are connected to the positive power supply (4 to 15 V), and VA− and VD− are connected to ground. The
AGND pin must be tied to V+/2. Furthermore, the half-supply node should be very “clean”, as any noise
appearing on it will be treated as an input to the filter. Ensure liberal bypassing is employed to reject any supply
noise and present a low impedance to the clock frequency. Bypass caps should always be located as close to
the supply pins a practical. Moreover, the regulator or op-amp approaches of generating V+/e is preferred for
very low clock frequency applications. The main power supply voltage should also be clean (preferably
regulated) and bypassed with 0.1-µF nonpolar ceramic capacitor. If there is no bulk cap nearby, a 10-uF
electrolytic tantalum in parallel with the 0.1-µF supply bypass cap should achieve cleaner and optimal transient
response. Select capacitors with low ESR and ESL rating and test them to ensure no ringing occurs. The power
source is preferably a linear supply or regulator. If a switching supply is used ensure it is a clean switcher and
deploy proper bypassing or post regulate with an LDO as necessary.
11 Layout
11.1 Layout Guidelines
The most critical part to the success of a switched capacitor filter design is a properly layout PCB. Because of
the mixed signal circuitry involved, take extra care in the board design for noise abatement, star-grounding, and
shielding techniques. A ground plane must separate digital and analog ground planes if possible, or have
separate paths and join together only at the common return node at the supply source. All component leads and
PCB tracks are kept as short as possible. The filter clock input should be a shielded cable.
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