LMF100_15 Datasheet, PDF (28/40 Pages) Texas Instruments – LMF100 Dual High-Performance Switched Capacitor Filters

LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
www.ti.com
Typical Application (continued)
If the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain
(Figure 35). As an example, a lowpass filter with a Q of 10 will have a 20-dB peak in its amplitude response at f₀.
If the nominal gain of the filter (H_OLP) is equal to 1, the gain at f₀ will be 10. The maximum input signal at f₀ must
therefore be less than 800 mV_p-p when the circuit is operated on ±5 volt supplies.
Also, one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 40). The notch output will be very small at f₀, so it might appear safe
to apply a large signal to the input. However, the bandpass will have its maximum gain at f₀ and can clip if
overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any
filter section, even ones whose outputs are not being directly used. Accompanying Figure 40 through Figure 50
are equations labeled circuit dynamics, which relate the Q and the gains at the various outputs. These should be
consulted to determine peak circuit gains and maximum allowable signals for a given application.
9.2.2.3 Offset Voltage
The switched capacitor integrators of the LMF100 have a slightly higher input offset voltage than found in a
typical continuous time active filter integrator. Because of TI's new LMCMOS process and new design techniques
the internal offsets have been minimized, compared to the industry standard MF10. Figure 59 shows an
equivalent circuit of the LMF100 from which the output DC offsets can be calculated. Typical values for these
offsets with S_A/B tied to V⁺ are:
V_OS1 = opamp offset = ±5 mV
V_OS2 = ±30 mV at 50:1 or 100:1
V_OS3 = ±15 mV at 50:1 or 100:1
When S_A/B is tied to V^−, V_OS2 will approximately halve. The DC offset at the BP output is equal to the input offset
of the lowpass integrator (V_OS3). The offsets at the other outputs depend on the mode of operation and the
resistor ratios, as described in the following expressions.
Mode 1 and Mode 4
V_OS(N)
=
V_OS1
æ
çè
1
Q
+
1+
H_OLP
ö
÷ø
-
V_OS3
Q
V_OS(BP)
= V_OS3
V_OS(LP)
= V_OS(N) - V_OS2
Mode 1a
V_OS (N.INV.BP)
V_OS (INV.BP)
V_OS (LP)
=
æçè₁₊
1
Q
ö
÷ø ^VOS1
-
V_OS3
Q
= V_OS3
= V_OS (N.INV.BP) - V_OS2
Mode 1b
V_OS(N)
V_OS(BP)
V_OS(LP)
=
V_OS1
æçè₁₊
R2
R3
+
R2
R1
ö
÷ø
-
R2
R3
V_OS3
= V_OS3
= ^VOS(N) - ^VOS2
2
2
Mode 2 and Mode 5
V_OS(N)
=
æ
ç
è
R2
Rp
+
ö
1_÷
ø
V_OS3
´
1+
1
R2
/
R4
+
V_OS2
1+
1
R4
/
R2
-
Q
V_OS3
1+ R2 / R4
: R_p
= R1|| R3 || R4
V_OS(BP)
= V_OS3
V_OS(LP)
= V_OS(N) - V_OS2
28
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