LMF100_15 Datasheet, PDF (8/40 Pages) Texas Instruments – LMF100 Dual High-Performance Switched Capacitor Filters

LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
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Electrical Characteristics for V⁺ = +2.5 V and V^− = −2.5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R₁ = R₃ = 100 k, R₂ = 10 k), V⁺ = +2.50 V and V^− = −2.50 V unless
otherwise specified. All limits are T_A = T_J = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
LMF100CCN
MIN
TYP
MAX
LMF100CIWM
MIN
TYP
MAX
UNIT
R_L = 5 k
All Outputs
1.6
−2.2
1.6
−2.2
V_OUT Minimum output voltage swing
R_L = 5 k (All
Outputs)
Tested
Limit⁽¹⁾
Design
Limit⁽²⁾
T_MIN to T_MAX
T_MIN to T_MAX
±1.5
V
±1.4
±1.4
R_L = 3.5 k
All Outputs
1.5
−2.1
1.5
V
−2.1
GB Operational amplifier gain BW
W product
5
5
MHz
SR Operational amplifier slew rate
18
18
V/µs
I_sc
Maximum output,
Source
Short circuit current⁽⁸⁾ _Sink
All Outputs
All Outputs
10
10
mA
20
20
mA
(8) The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
6.7 Logic Input Characteristics
All limits apply to T_A = T_J = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN Logical “1” V⁺ = +5 V, V^− = −5 V,
CMOS Clock
Input Voltage
MAX Logical “0” V_LSh = 0 V
MIN Logical “1” V⁺ = +10 V, V^− = 0 V,
MAX Logical “0” V_LSh = +5 V
MIN Logical “1” V⁺ = +5 V, V^− = −5 V,
TTL Clock
Input Voltage
MAX Logical “0” V_LSh = 0 V
MIN Logical “1” V⁺ = +10 V, V^− = 0 V,
MAX Logical “0” V_LSh = 0 V
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
Tested Limit⁽¹⁾
Design Limit⁽²⁾
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
T_MIN to T_MAX
LMF100CCN
MIN TYP MAX
3
3
−3
−3
8
8
2
2
2
2
0.8
0.8
2
2
0.8
0.8
LMF100CIWM
UNIT
MIN
TYP MAX
3V
–3 V
8V
2V
2V
0.8 V
2V
0.8 V
(1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
(2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
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