DS90UB927-Q1 Datasheet, PDF (9/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
www.ti.com
SNLS416B – JUNE 2012
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. ^{(1) (2) (3)}
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
FPD-Link LVDS Input
t_RSP
Receiver Strobe Position
Figure 6
RxCLKIN±, 0.25
0.5
0.75
RXIN[3:0]±
FPD-Link III CML IO
t_LHT
CML Output Low-to-High
Transition Time
t_HLT
CML Output High-to-Low
Transition Time
t_PLD
Serializer PLL Lock Time
Figure 5
(4)_{Figure 7}
DOUT+,
DOUT-
PCLK =
5MHz to
85MHz
100
140
100
140
5
t_SD
Delay — Latency
Output Total Jitter,
t_TJIT
Bit Error Rate ≤1E-9
Figure 9 ^{(5) (6) (7) (8) (9)}
Figure 8
Checkerboard Pattern
PCLK=5MHz
Figure 10
Checkerboard Pattern
PCLK=85MHz
Figure 10
RxCLKIN±
146*T
0.17
0.2
0.26
0.29
f/40 < Jitter Freq < f/20, DES =
t_IJIT
Input Jitter Tolerance, Bit Error
Rate ≤1E-9
(10) (6)
DS90UH926Q
f/40 < Jitter Freq < f/20, DES =
RxCLKIN±, f
= 78MHz
DS90UB928Q
0.6
0.5
I2S Receiver
T_I2S
I2S Clock Period
Figure 12, ^{(5) (11)}
RxCLKIN± f=5MHz to 85MHz
I2S_CLK,
PCLK =
5MHz to
85MHz
>4/PCL
K or
>77
T_HC
I2S Clock High Time
Figure 12 ⁽¹¹⁾
I2S_CLK
0.35
T_LC
I2S Clock Low Time
Figure 12 ⁽¹¹⁾
I2S_CLK
0.35
t_sr
I2S Set-up Time
Figure 12
I2S_WC
0.2
I2S_D[A,B,C,
D]
t_htr
I2S Hold Time
Figure 12
I2S_WC
0.2
I2S_D[A,B,C,
D]
Other I/O
Units
UI
ps
ps
ms
ns
UI
UI
UI
UI
ns
T_I2S
T_I2S
T_I2S
T_I2S
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Typical values represent most likely parametric norms at V_DD33 = 3.3V, V_DDIO = 1.8V or 3.3V, Ta = +25 degC, and at the Recommended
Operation Conditions at the time of product characterization and are not guaranteed.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except V_OD and ΔV_OD, which are differential voltages.Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal
signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing
of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50MHz.
(4) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.
(5) Specification is guaranteed by design and is not tested in production
(6) Specification is guaranteed by characterization and is not tested in production
(7) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.
(8) Output jitter specs are dependent upon the input clock jitter at the SER
(9) t_TJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±
(10) Jitter Frequency is specified in conjunction with DS90UB928Q PLL bandwidth.
(11) I2S specifications for t_LC and t_HC pulses must each be greater than 2 PCLK periods to guarantee sampling and supersedes the
0.35*T_{I2S_CLK} requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK
Copyright © 2012, Texas Instruments Incorporated
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