DS90UB927-Q1 Datasheet, PDF (41/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

www.ti.com
ADD
(dec)
23
ADD
(hex)
0x17
Register Name
I2C Control
24
0x18 SCL High Time
25
0x19 SCL Low Time
26
0x1A Data Path Control 2
27
0x1B BIST BC Error Count
DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
Table 5. Serial Control Bus Registers (continued)
Bit(s)
7
6:4
3:0
7:0
7:0
7
6:1
0
7:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
R
Default
(hex)
0x1E
0xA1
0xA5
0x00
0x00
Function
Description
I2C Pass All
SDA Hold Time
I2C Filter Depth
SCL HIGH Time
SCL LOW Time
Block I2S Auto
Config
I2S Surround
BIST BC Errorr
Pass All
0: Enable Forward Control Channel pass-through only of I2C
accesses to I2C Slave IDs matching either the remote Deserializer
Slave ID or the remote Slave ID. (default)
1: Enable Forward Control Channel pass-through of all I2C accesses
to I2C Slave IDs that do not match the Serializer I2C Slave ID.
Internal SDA Hold Time
Configures the amount of internal hold time provided for the SDA input
relative to the SCL input. Units are 40 nanoseconds.
Configures the maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 5 nanoseconds.
I2C Master SCL High Time
This field configures the high pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. Units are 40 ns for the
nominal oscillator clock frequency.
I2C SCL Low Time
This field configures the low pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. This value is also used
as the SDA setup time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional Control Channel.
Units are 40 ns for the nominal oscillator clock frequency.
Block automatic I2S mode configuration
(repeater only)
0: I2S mode (2-channel, 4-channel, or surround) is detected from the
in-band audio signaling
1: Disable automatic detection of I2S mode
Reserved
Enable 5.1- or 7.1-channel I2S audio transport
0: 2-channel or 4-channel I2S audio is enabled as configured in
register 0x12 bits 3 and 0 (default)
1: 5.1- or 7.1-channel audio is enabled
Note that I2S Data Island Transport is the only option for surround
audio. Also note that in a repeater, this bit may be overridden by the
in-band I2S mode detection.
BIST Back Channel CRC Error Counter
This register stores the back-channel CRC error count during BIST
Mode (saturates at 255 errors). Clears when a new BIST is initiated or
by 0x04[5]
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DS90UB927-Q1 DS90UB927Q DS90UB927Q-Q1
Submit Documentation Feedback
41