DS90UB927-Q1 Datasheet, PDF (17/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
RxCLKIN +/-
RxIN3 +/-
RxIN2 +/-
RxIN1 +/-
RxIN0 +/-
Previous cycle
Current cycle (PCLK Period)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
R[1]
(bit 22)
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
B[6]
(bit 16)
B[5]
(bit 15)
R[0]
(bit 21)
B[4]
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
Figure 14. FPD-Link Mapping: LSBs on RxIN3 (MAPSEL=L)
G[3]
(bit 7)
R[2]
(bit 0)
RxCLKIN +/-
RxIN3 +/-
Previous cycle
RxIN2 +/-
Current cycle (PCLK Period)
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
R[6]
(bit 21)
B[2]
(bit 14)
RxIN1 +/-
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
RxIN0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 15. FPD-Link Mapping: MSBs on RxIN3 (MAPSEL=H)
VIDEO CONTROL SIGNALS
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the DS90UB927Q applies a minimum pulse width filter
on these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 5. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 5. DE can have at most two transitions per 130 PCLKs.
Copyright © 2012, Texas Instruments Incorporated
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