DS90UB927-Q1 Datasheet, PDF (4/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
www.ti.com
Pin Name
Pin #
I/O, Type Description
BKWD
22
I, LVCMOS Backward Compatible Mode Select
w/ pull down BKWD = 0, interfacing to DS90UH926/8Q (Default)
BKWD = 1, interfacing to DS90UR906/8Q, DS90UR916Q
Requires a 10kΩ pull-up if set HIGH
MAPSEL
23
I, LVCMOS FPD-Link Input Map Select
w/ pull down MAPSEL = 0, LSBs on RxIN3± (Default)
MAPSEL = 1, MSBs on RxIN3±
See Figure 14and Figure 15
Requires a 10kΩ pull-up if set HIGH
LFMODE
25
I, LVCMOS Low Frequency Mode Select
w/ pull down LFMODE = 0, 15MHz ≤ RxCLKIN ≤ 85MHz (Default)
LFMODE = 1, 5MHz ≤ RxCLKIN < 15MHz
Requires a 10kΩ pull-up if set HIGH
Optional Parallel Interface
GPIO[3:2]
6, 5
I/O, LVCMOS General Purpose I/O
w/ pull down Shared with I2S_DD and I2S_DC
See Table 1
GPIO_REG[
8:5]
2, 1, 3, 4
I/O, LVCMOS Register-Only General Purpose I/O
w/ pull down Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
See Table 2
Control and Configuration
PDB
SCL
18
I, LVCMOS Power-down Mode Input Pin
w/ pull-down Must be driven or pulled up to V_DD33. Refer to “Power Up Requirements and PDB Pin" in the
Applications Information Section.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and I_DD is minimized. Control Registers are RESET.
9
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pull-up to V_DD33. DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
10
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pull-up to V_DD33. DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
IDx
11
I, Analog I2C Address Select
External pull-up to V_DD33 is required under all conditions. DO NOT FLOAT.
Connect to external pull-up to V_DD33 and pull-down to GND to create a voltage divider.
See Figure 25and Table 4
Status
INTB
27
FPD-Link III Serial Interface
O, LVCMOS
Open Drain
Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7kΩ to V_DDIO. DO NOT FLOAT.
DOUT+
17
I/O, LVDS True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
16
I/O, LVDS Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
20
Power⁽¹⁾ and Ground
Analog
Common Mode Filter.
Connect 0.1µF to GND (required)
VDD33_A
19
VDD33_B
26
Power Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7µF capacitor to GND
VDDIO
7, 24
Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7µF capacitor to GND
GND
DAP
Ground
Large metal contact at the bottom center of the device package Connect to the ground
plane (GND) with at least 9 vias.
Regulator Capacitor
(1) The V_DD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
4
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