DS90UB927-Q1 Datasheet, PDF (16/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
www.ti.com
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel is composed of a 35-bit frame containing RGB data, sync signals, I2C, and
I2S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the serial stream generated per PCLK
cycle into RxCLKIN±. This data payload is optimized for signal transmission over an AC coupled link. Data is
randomized, DC-balanced and scrambled.
C1
C0
Figure 13. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5MHz to 15MHz (LFMODE=1) and 15MHz to 85MHz (LFMODE=0).
This corresponds to an application payload rate range of 155Mbps to 2.635Gbps, with an actual line rate range
of 525Mbps to 2.975Gbps.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Back Channel of the DS90UB927Q provides bidirectional communication between the display
and host processor. Data is transferred simultaneously over the same physical link as the high-speed forward
channel data. The back channel transports I2C, CRC, and 4 bits of standard GPIO information with a 10Mbps
line rate.
BACKWARD COMPATIBLE MODE
The DS90UB927Q is also backward compatible to DS90UR906Q, DS90UR908Q FPD, and DS90UR916Q FPD-
Link II deserializers for PCLK frequencies ranging from 5MHz to 65MHz. It is also backward compatible with the
DS90UR910Q for PCLK frequencies ranging from 5MHz to 75MHz. The serializer transmits 28-bits of data over
a single serial FPD-Link II pair operating at a payload rate of 120Mbps to 1.8Gbps, corresponding to a line rate
of 140Mbps to 2.1Gbps. The Backward Compatibility configuration can be selected through the BKWD pin or
programmed through the configuration register (Table 5). The bidirectional control channel,, bidirectional GPIOs,
I2S, and interrupt (INTB) are not active in this mode. However, local I2C access to the serializer is still available.
Note: PCLK frequency range in this mode is 15MHz to 75MHz for LFMODE=0 and 5MHZ to <15MHz for
LFMODE=1.
COMMON MODE FILTER PIN (CMF)
The serializer provides access to the center tap of the internal CML termination. A 0.1μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 29). This
increases noise rejection capability in high-noise environments.
FPD-LINK INPUT FRAME AND COLOR BIT MAPPING SELECT
The DS90UB927Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs
on RxIN[3]±, shown in Figure 14, or MSBs on RxIN[3], shown in Figure 15. Each frame corresponds to a single
pixel clock (PCLK) cycle. The LVDS clock input to RxCLKIN± follows a 4:3 duty cycle scheme, with each 28-bit
pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping
scheme is controlled by MAPSEL pin or by Register (Table 5).
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