DS90UB927-Q1 Datasheet, PDF (26/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
www.ti.com
Step 2: The DS90UB927Q serializer is awakened through the back channel if it is not already on. An all-zeros
pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once
the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the
deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected,
the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If
there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is
held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-
controlled and may be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 24 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.),
thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing
signal condition enhancements (Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 23. BIST Mode Flow Diagram
FORWARD CHANNEL AND BACK CHANNEL ERROR CHECKING
While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all
zeroes pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing, etc. and is transmitted over
the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the recovered serial
stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on the
PASS pin of the deserializer.
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x0C[0] - Table 5). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters BIST mode. As soon as the serializer enters
BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode
CRC error register is active in BIST mode only and keeps a record of the last BIST run until cleared or the
serializer enters BIST mode again.
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