DS90UB927-Q1 Datasheet, PDF (25/56 Pages) Texas Instruments – 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

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DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1
SNLS416B – JUNE 2012
L3 < 60 mm
TX
(UB927)
RX
(UB928)
R1=100
R2=100
L1 < 75 mm
L2 < 60 mm
TX
(UB927)
L3 < 60 mm
TX
(UB927)
Figure 22. FPD-Link Fan-Out Electrical Requirements
BUILT IN SELF TEST (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-
speed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
BIST CONFIGURATION AND STATUS
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back
Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST.
See Figure 23 for the BIST mode flow diagram.
SAMPLE BIST SEQUENCE
Step 1: For the DS90UB927Q paired with a FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN pin
of Deserializer. The desired clock source is selected through the deserializer BISTC pin.
Copyright © 2012, Texas Instruments Incorporated
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