DS125DF410_13 Datasheet, PDF (8/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. ⁽¹⁾
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T_SKEW
Intra Pair Skew
Difference in 50% crossing between
TXPn and TXNn for any output
3
ps
CLOCK AND DATA RECOVERY
BW_PLL
J_TOL
J_TRANS
PLL Bandwidth
-3 dB
Input sinusoidal jitter tolerance
10 kHz to 250 MHz sinusoidal jitter
frequency
Jitter Transfer
Sinusoidal jitter at 10 MHz jitter
frequency
Measured at 10.3125 Gbps
Measured at BER = 10^-15
Measured at BER = 10^-15
5
MHz
0.6
UI
-6
dB
T_LOCK
CDR Lock Time,
Fixed (manual setting) of CTLE, DFE
Ref_mode 3,
HEO/VEO lock monitor disabled
2
ms
Fixed Data Rate (eg. 10.3125
(register 0x3e, bit 7 set to 0)
Gbps)
Fixed (manual setting) of CTLE, DFE
HEO/VEO lock monitor enabled
12
ms
(register 0x3e, bit 7 set to 1 - default)
Medium (20 inch) channel loss with
CTLE and DFE adaption,
HEO/VEO lock monitor must be
enabled ⁽¹³⁾
74
ms
(13) The CDR lock time is when the input has a valid signal to when the output sends retimed data. The CDR lock time is after the CTLE
adaption is completed. In adapt_mode 2 or 3, the DFE adaption will continue after the CDR lock time.
8
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