DS125DF410_13 Datasheet, PDF (10/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
www.ti.com
The CTLE is a four-stage variable boost high-gain amplifier with a quasi-high-pass characteristic. Each of the
four stages can be set to provide various amounts of high-frequency boost with the overall transfer function of
the CTLE set by the cascade of all four sections. The high-frequency boost of each CTLE stage is variable. The
optimum boost for each stage is one that causes the transfer function magnitude of the transmission channel and
the CTLE in cascade to be flat over a band of frequencies extending up to half the data rate which is commonly
referred to as the “Nyquist” frequency. In normal operation, the DS125DF410 sets the boost of the CTLE
automatically to approximate the optimum cascaded response.
In addition to the CTLE, the DS125DF410 includes a clock-based Decision-Feedback Equalizer or DFE. The
DFE operates as a symbol-spaced, discrete-time, analog filter which provides additional discrimination against
signal impairments, both those arising from the dispersive transmission channel between the transmitter and the
DS125DF410 and those arising from noise in the system and crosstalk between transmission channels. The DFE
introduces an analog summing node between the CTLE output and the comparator, which makes the “decision”
whether the current bit is a 1 or a 0. At this summing node scaled versions of the previous five bits are added in
an analog fashion to the current bit, and the output of the summing node is the input to the comparator. This is a
well-known type of discrete-time filter implementation.
The scaling or tap weight of each of the five taps of the DFE can be set by a four- or five-bit register setting and
the algebraic sign of each tap weight is set by another bit. In general, the higher the tap weight setting the larger
the scaling factor for each bit is.
The CTLE and the DFE provide a significant improvement in the bit error rate performance for retimed data
transmitted through lossy transmission media. However, it is important to configure the CTLE and DFE properly
with the correct boost settings and tap weights and polarities. Otherwise, the CTLE and DFE will not provide the
bit error rate performance benefits they are capable of providing, and they may even degrade the bit error rate.
The ideal settings for the CTLE and DFE precisely cancel the non-ideal characteristics of the transmission
media.
To make configuration of these settings easier, the DS125DF410 is designed to determine the correct settings
for the CTLE and DFE autonomously by automatically adapting these equalizations to the input transmission
media. The automatic adaptation takes place when a signal is first detected at the input to the DS125DF410,
immediately after the DS125DF410 acquires phase lock. The automatic adaptation is also triggered whenever
the CDR circuitry is reset.
The DS125DF410 uses its internal eye monitor to generate a figure of merit for the adaptation. The DS125DF410
adjusts its CTLE boost settings and its DFE tap weights and polarities in a systematic way to optimize this figure
of merit.
The DS125DF410 is designed for operation with a default figure of merit. However, if desired, the figure of merit
may be configured by the user independently for each channel. This will affect the values to which the equalizers
will adapt.
The automatic adaptation may be initiated at any time by the user over the SMBus and the values obtained by
the DS125DF410 may be observed or modified over the SMBus
In the case of the CTLE, a subset of all the available boost settings are used for the adaptation. Because of the
cascaded architecture of the CTLE, there are multiple boost settings that provide almost the same CTLE
frequency response. A subset of the available boost settings is pre-programmed into the DS125DF410 and it is
this subset that is searched during CTLE adaptation. The subset of boost settings to be searched is user-
configurable by register writes over the SMBus.
Clock and Data Recovery
The DS125DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming
data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit
transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the
bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125DF410 in a
system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the
system.
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