DS125DF410_13 Datasheet, PDF (36/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
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Setting the Adaptation/Lock Mode
Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0,
Register 0x3e, bit 7, and Register 0x6a
There are four adaptation modes available in the DS125DF410.
• Mode 0: The user is responsible for setting the CTLE and DFE values. This mode is used if the transmission
channel response is fixed.
• Mode 1: Only the CTLE is adapted to equalize the transmission channel. The DFE is enabled, but the tap
weights are all set to 0. This mode is primarily used for smoothly-varying high-loss transmission channels
such as cables and simple PCB traces.
• Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections,
and crosstalk in the input transmission channel.
– The maximum DFE tap weights can be constrained using register 0x34, bits 3:0, and register 0x35, bits
4:0 as shown in Table 7.
• Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more
emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission
channels.
Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the
adaptation algorithm is shown in Table 13.
Register 0x31, Bit 6
adapt_mode[1]
0
0
1
1
Table 13. DS125DF410 Adaptation Algorithm Settings
Register 0x31, Bit 5
adapt_mode[0]
0
1
0
1
Adapt Mode Setting <1:0>
00
01
10
11
Adaptation Algorithm
No Adaptation
Adapt CTLE Until Optimum
(Default)
Adapt CTLE Until Optimum then
DFE, then CTLE Again
Adapt CTLE Until Lock, then
DFE, the CTLE Again
By default the DS125DF410 requires that the equalized internal eye exhibit horizontal and vertical eye openings
greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register
0x6a.
The DS125DF410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye
opening falls below the threshold set in register 0x6a, the DS125DF410 will declare a loss of lock.
The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of
register 0x3e.
Initiating Adaptation
Register 0x24, bit 2, and Register 0x2f, bit 0
When the DS125DF410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is
selected using bits 6:5 in register 0x31, the DS125DF410 will also try to adapt its CTLE and its DFE.
Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing
register 0x2f, bit 0. In the DS125DF410, DFE adaptation can be initiated by setting and then clearing bit 2 of
register 0x24.
Setting the Reference Enable Mode
Register 0x36, bits 5:4
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a
value of 3 or 2'b11.
A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference
clock in the DS125DF410 is explained below.
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