DS125DF410_13 Datasheet, PDF (26/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Address (Hex) Bits
0x6a
7:4
3:0
0x6b
7:0
0x6c
7:0
0x6d
7:0
0x6e
7
6
0x70
2:0
0x71
5
4:0
0x72
4
3:0
0x73
4
3:0
0x74
4
3:0
0x75
4
3:0
Table 7. Channel Registers (continued)
Default Value (Hex) Mode
0x4
R/W
0x4
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x3
R/W
0x0
R
0x00
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
Field Name
veo_lck_thrsh[3:0]
heo_lck_thrsh[3:0]
fom_a[7:0]
fom_b[7:0]
fom_c[7:0]
en_new_fom_ctle
en_new_fom_dfe
eq_lb_cnt[2:0]
dfe_pol_1_obs
dfe_wt1_obs[4:0]
dfe_pol_2_obs
dfe_wt2_obs[3:0]
dfe_pol_3_obs
dfe_wt3_obs[3:0]
dfe_pol_4_obs
dfe_wt4_obs[3:0]
dfe_pol_5_obs
dfe_wt5_obs[3:0]
Description
Vertical Eye Opening Lock Threshold
<3:0>
Horizontal Eye Opening Lock Threshold
<3:0>
Adaptation Figure of Merit Term a<7:0>
Adaptation Figure of Merit Term b<7:0>
Adaptation Figure of Merit Term c<7:0>
Enable Alternate Figure of Merit for CTLE
Adaptation
Enable Alternate Figure of Merit for DFE
Adaptation
CTLE Adaptation Look-Beyond Count
<2:0>
DFE Tap 1 Polarity (Read Only)
DFE Tap 1 Weight (Read Only) <4:0>
DFE Tap 2 Polarity (Read Only)
DFE Tap 2 Weight (Read Only) <3:0>
DFE Tap 3 Polarity (Read Only)
DFE Tap 3 Weight (Read Only) <3:0>
DFE Tap 4 Polarity (Read Only)
DFT Tap 4 Weight (Read Only) <3:0>
DFE Tap 5 Polarity (Read Only)
DFE Tap 5 Weight (Read Only) <3:0>
Resetting Individual Channels of the Retimer
Register 0x00, bit 2, and register 0x0a, bits 3:2
Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory
default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the
DS125DF410 since it was powered-up.
To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and
adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the
reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same
operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal
is present at the input to the selected channel, the DS125DF410 will attempt to lock to it and will adapt its CTLE
and its DFE according to the currently configured adapt mode for the selected channel. The adapt mode is
configured by channel register 0x31, bits 6:5.
Interrupt Status
Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and
Register 0x36, bit 6
Each channel of the DS125DF410 will generate an interrupt under several different conditions. The DS125DF410
will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the
HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when
the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one
of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional
details via register reads over the SMBus.
First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer
has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any
retimer generates an interrupt the system controller can be notified using a single interrupt input.
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