DS125DF410_13 Datasheet, PDF (14/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
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Finally, register 0x64 should be set to a value of 0xff. This is the PPM count tolerance. The resulting tolerance in
parts per million is given by Tol_PPM = (1 X 10^-6 X N_TOL) / N_PPM. In this equation, N_TOL is the 4-bit tolerance value
loaded into the upper or lower four bits of register 0x64. For the example we are using here, both of these values
are 0xf, or decimal 15. For a PPM count value of 12,800, for Group 0, this yields a tolerance of 1172 parts per
million. For a PPM count value of 13,200, for Group 1, this yields a tolerance of 1136 parts per million.
These tolerance values can be reduced if it is known that the frequency accuracy of the system and of the 25
MHz reference clock are very good. For most applications, however, a value of 0xff in register 0x64 will give
robust performance.
For all the other standards shown in Table 1 the expected PPM count for Group 0 (registers 0x60 and 0x61) and
Group 1 (registers 0x62 and 0x63) will be set the same, since there is only one VCO frequency for these
standards. The expected PPM count and tolerance are computed as described above for 10 GbE and 1 GbE.
The same values are written to each pair of PPM count registers for these standards.
As is the case with the standards-based mode of operation, the expected PPM count value and the PPM count
tolerance must be written to registers 0x60, 0x61, 0x62, 0x63, and 0x64. These are computed exactly as
described above for the standards-based mode of operation. Since the frequency-range-based mode of
operation uses both Group 0 and Group 1 with the same expected PPM count, the same values should be
loaded into the pairs of registers 0x60 and 0x62, and 0x61 and 0x63.
As an example, suppose that the expected data rate is 8.5 Gbps. The VCO frequency for the frequency-range
based mode of operation is also 8.5 GHz. So we compute N_PPM = 8.5 X 1280 = 10,880. This is a decimal value.
In hexadecimal this is 0x2a80.
We write the lower-order byte, 0x80 into registers 0x60 and 0x62. We write the higher order byte, 0x2a, into the
least-significant 7 bits of registers 0x61 and 0x63. We also set bit 7 of registers 0x61 and 0x63. When this
operation is complete, registers 0x60 and 0x62 will contain a value of 0x80. Registers 0x61 and 0x63 will contain
a value of 0xaa.
We also write the PPM tolerance into both the upper and lower four bits of register 0x64. If we write this register
to a value of 0xff, then the PPM count tolerance in parts per million will be given by Tol_PPM = (1 X 10^-6 X N_TOL) /
N_PPM = 1379 parts per million. This value will be appropriate for most systems.
In summary, for data rates that correspond to the pre-defined standards for the DS125DF410, the standards-
based mode of operation can be used. This mode offers automatic switching of the divide ratio (and, for 10 GbE
and 1 GbE, the VCO frequency) to easily accommodate operation over harmonically-related data rates. For data
rates that are not covered by the pre-defined standards, the frequency-range-based mode of operation can be
used. This mode works with a fixed divider ratio, which is nominally 1. However, the divider ratio can be forced to
other values if desired.
The register configuration procedure is as follow:
1. Select the desired channel of the DS125DF410 by writing the appropriate value to register 0xff.
2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described above to enable the 25 MHz reference clock.
3. Write registers 0x2f with the correct values.
4. Compute the expected PPM count values for Group 0 and Group 1 as described above.
5. Write the expected PPM count values into registers 0x60-0x63 as described above, setting bit 7 of both
registers 0x61 and 0x63.
6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM.
7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a.
If there is a signal at the correct data rate present at the input to the DS125DF410, the retimer will lock to it.
In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the
DS125DF410 determines the correct CAP DAC values automatically.
Because it is not necessary to set the CAP DAC values for Group 0 and Group 1 a-priori in ref_mode 3, the
DS125DF410 can be set up to use automatically switching divider ratios and arbitrary VCO frequencies in this
mode. The mapping of values in register 0x2f, bits 7:4, versus the divider ratios used for each of the two groups
is shown in Table 2.
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