DS125DF410_13 Datasheet, PDF (35/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
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SNLS398E – JANUARY 2012 – REVISED MAY 2013
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.
Setting this bit will approximately double the nominal rise and fall times of the DS125DF410 output driver. This bit
is cleared by default.
Inverting the Output Polarity
Register 0x1f, bit 7
In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes
necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.
The DS125DF410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of
register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility
in system design and board layout.
Overriding the Figure of Merit for Adaptation
Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e,
bits 7 and 6
The default figure of merit for both the CTLE and DFE adaptation in the DS125DF410 is simple. The horizontal
and vertical eye openings are measured for each CTLE boost setting or set of DFE tap weights and polarities.
The vertical eye opening is scaled to a constant reference vertical eye opening and the smaller of the horizontal
or vertical eye opening is taken as the figure of merit for that set of equalizer settings. The objective is to adapt
the equalizer to a point where the horizontal and vertical eye openings are both as large as possible. This usually
provides optimum bit error rate performance for most transmission channels.
In some systems the adaptation can reach a better setting if only the horizontal or vertical eye opening is used to
compute the figure of merit rather than using both. This will be system-dependent and the user must determine
through experiment whether this provides better adaptation in the user's system. For the DS125DF410, the DFE
figure of merit type can be set using register 0x2c, bits 5:4. The value of this two-bit field versus the configured
figure of merit type is shown in Table 12.
Register 0x2c, bits 5:4
0x0
0x1
0x2
0x3
Table 12. Figure of Merit Type Setting
Figure of Merit Type
Not Valid
Only HEO is used
Only VEO is used
Both HEO and VEO are used (default)
The CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 4:3, with the same effect as
in Table 12.
For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The
DS125DF410 includes the capability of adapting based on a configurable figure of merit. The configurable figure
of merit is structured as shown in the equation below.
FOM = (HEO – b) x a + (VEO – c) x (1 – a)
In this equation, HEO is horizontal eye opening, VEO is vertical eye opening, FOM is the figure of merit, and the
factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively.
In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of
merit for the CTLE adaptation, set bit 7 of register 0x6e, the en_new_fom_ctle bit. To use the configurable figure
of merit for the DFE adaptation (in the DS125DF410), set bit 6 of register 0x6e, the en_new_fom_dfe bit. The
same scaling factors are used for both CTLE and DFE adaptation when the configurable figure of merit is
enabled.
Setting the Rate and Subrate for Lock Acquisition
Register 0x2f, bits 7:6 and 5:4
The rate and subrate settings, which constrain the data rate search in order to reduce lock time, can be set using
channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>. These four bits form a hex digit
which matches the codes in Table 1.
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