DS125DF410_13 Datasheet, PDF (29/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
Input Signal Status
Present
Table 8. Default Output Status Description (continued)
Channel Status
Locked
Output Status
Retimed Data
This default behavior can be modified by register writes.
Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the
corresponding meanings of each are shown in Table 9.
Bit Field Value
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 9. Output Multiplexer Override Settings
Output Multiplexer Setting
Mute
N/A
10 MHz Clock
PRBS Generator
VCO Q-Clock
VCO I-Clock
Retimed Data
Raw Data
Comments
Default when no signal is present or when
the retimer is unlocked
Invalid Setting
Internal 10 MHz clock
Clock frequency may not be precise, There is
no production test coverage for this and is
only use for testing.
PRBS Generator must be enabled to output
PRBS sequence
Register 0x09, bit 4, and register 0x1e, bit 0,
must be set to enable the VCO Q-Clock.
There is no production test coverage for this
and is only use for testing.
There is no production test coverage for this
and is only use for testing.
Default when the retimer is locked
Bypass the CDR, output is not retimed and
must set bit 5 of register 0x09 and bit 7 of
0x3F.
If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register
0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The
default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input
signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data (not retimed)
when it is not locked to its input signal.
Set the override bit to 1, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field
in register 0x1e, bits 7:5. In the raw data mode (CDR is bypassed), the register 0x3F, bit 7 should be set to 1,
this will disable the fast cap re-search which stops the output from powering down (muting) during raw mode.
When no signal is present at the input to the selected channel of the DS125DF410 the signal detect circuitry will
power down the channel. This includes the output driver which is therefore muted when no signal is present at
the input. If you want to get an output when no signal is present at the input, for example to enable a free-
running PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set
bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel
will be enabled. If the channel was disabled before, the current drain from the supply will increase by 100–150
mA depending upon the other channel settings in the device. This increased current drain indicates that the
channel is now enabled.
The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register
0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the
output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device
output may saturate to a static 1 or 0.
If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC
settings and it will vary from part to part and over temperature.
If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate
determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal
is present at the input and the DS125DF410 can lock to it, the output of the PRBS generator will be synchronous
with the input signal, but the bit stream output will be determined by the PRBS generator selection.
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