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DS125DF410_13 Datasheet, PDF (6/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer
DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER
PD
Power Supply Consumption
Average Power Consumption (DFE
Powered-Up and Enabled)(2)
720
mW
NTPS
Supply Noise Tolerance(4)
2.5V LVCMOS DC SPECIFICATIONS
Max Transient Power Supply
Current (3)
50 Hz to 100 Hz
100 Hz to 10 MHz
10 MHz to 5.0 GHz
500
610
mA
100
mVP-P
40
mVP-P
10
mVP-P
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
IOH = -3mA
VOL
Low Level Output Voltage
IOL = 3mA
IIN
Input Leakage Current
VIN = VDD
VIN = GND
IIH
Input High Current (EN_SMB pin) VIN = VDD
IIL
Input Low Current (EN_SMB pin) VIN = GND
3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)
1.75
GND
VDD
V
0.7
V
2.0
V
0.4
V
+10
μA
-10
μA
+55
μA
-110
μA
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOL
Low Level Output Voltage
IIH
Input High Current
IIL
Input Low Current
fSDC
SMBus clock rate
DATA BIT RATES
VDD = 2.5 V
VDD = 2.5 V
IPULLUP = 3mA
VIN = 3.6 V, VDD = 2.5V
VIN = GND, VDD = 2.5V
1.75
GND
+20
-10
100
3.6
V
0.7
V
0.4
V
+40
μA
+10
μA
400
KHz
RB
Bit Rate Range
SIGNAL DETECT
9.8
12.5
Gbps
SDH
Signal Detect ON Threshold Level Default input signal level to assert
70
signal detect, 10.3125 Gbps, PRBS-
31
mVp-p
SDL
Signal Detect OFF Threshold Level Default input signal level to de-assert
10
signal detect, 10.3125 Gbps, PRBS-
31
mVp-p
(1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization.
(2) VDD= 2.5V, TA = 25°C. All four channels active and locked. DFE is powered-up and enabled.
(3) Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power
rating during the time required to acquire CDR lock.
(4) Allowed supply noise (mVP-P sine wave) under typical conditions.
6
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