DS125DF410_13 Datasheet, PDF (13/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
www.ti.com
SNLS398E – JANUARY 2012 – REVISED MAY 2013
Standards-Based Modes
The DS125DF410 is designed to automatically operate with various multi-band data standards.
The first set of register writes constrain the coarse VCO tuning and the VCO divider ratios. When these registers
are set as indicated in Table 1, the DS125DF410 restricts its coarse VCO tuning to a set of coarse tuning values.
It also restricts the VCO divider ratio to the set of divider ratios required to cover the frequency bands for the
desired data rate standard. This enables the DS125DF410 to acquire phase lock more quickly than would be
possible if the coarse tuning range were unrestricted.
Standards
InfiniBand
CPRI1
CPRI2
PROP3
Interlaken1
Interlaken2
Ethernet
Table 1. Standards-Based Modes Register Settings
Data Rates (Gb/s)
VCO Frequencies (GHz)
2.5, 5, 10
10.0
2.4576, 4.9152, 9.8304 9.8304
3.072, 6.144
12.288
6.25
12.5
3.125, 6.25
12.5
10.3125
10.3125
1.25, 10.3125
10.0, 10.3125
Divider Ratios
1, 2, 4
1, 2, 4
2, 4
2
2, 4
1
1, 8
Register 0x2F Value (hex)
0x24
0x34
0x44
0xA4
0xB4
0xC4
0xF4
As an example of the usage of the registers in Table 1, assume that the retimer is required to operate in 10 GbE
or 1GbE mode. By setting register 0x2f, bits 7:4, to 4'b1111, the DS125DF410 will automatically set its divider
ratio and its coarse VCO tuning setting to lock to either a 10 GbE signal (at 10.3125 Gb/s) or a 1 GbE signal (at
1.25 Gb/s) at its input.
For some standards shown in the table above, the required VCO frequency is the same for each data rate in the
standard. Only the divider ratios are different. The retimer can automatically switch between the required divider
ratios with a single set of register settings.
For other data rates, it is also necessary to set the expected PPM count and the PPM count tolerance. These are
the values the retimer uses to detect a valid frequency lock.
For the 10 GbE and 1 GbE mode shown in the table above, two frequency groups are defined. These two
frequency groups are referred to as “Group 0”, for 1 GbE, and “Group 1”, for 10 GbE. This same frequency group
structure is present for all frequency modes, but for some modes the expected frequency for both groups is the
same. The expected PPM count information for Group 0 is set in registers 0x60 and 0x61. For Group 1, it is set
in registers 0x62 and 0x63. For both groups, the PPM count tolerance is set in register 0x64.
The value of the PPM count for either group is computed the same way from the expected data rate in Gbps,
R_Gbps. The PPM count value, denoted N_PPM, is computed by N_PPM = R_Gbps X 1280.
As an example we consider the PPM count setup for 10 GbE and 1 GbE. The expected PPM count for Group 0,
which in this case is 1 GbE, is set in registers 0x60 and 0x61. The expected VCO frequency for 1 G is 10.0 G.
The actual data rate for 1 GbE, which is 8B/10B coded, is 1.25 Gbps. With a VCO divide ratio of 8, which is the
divide ratio automatically used by the retimer for 1 GbE, this yields a VCO frequency of 10.0 GHz.
We compute the PPM count as N_PPM = 10.0 X 1280 = 12,800. This is a decimal value. In hexadecimal, this is
0x3200.
The lower-order byte is loaded into register 0x60. The higher order byte, 0x32, is loaded into the 7 least
significant bits of register 0x61. In addition, bit 7 of register 0x61 is set, indicating manual load of the PPM count.
When this is complete, register 0x60 will contain 0x00. Register 0x61 will contain 0xb2.
For the example we are considering, Group 1 is for 10 GbE. Here the actual data rate for the 64/66B encoded 10
GbE data is 10.3125 Gbps. For 10 GbE, the retimer automatically uses a divide ratio of 1, so the VCO frequency
is also 10.3125 GHz. For 10 GbE, we compute the expected PPM count as N_PPM = 10.3125 X 1280 = 13,200.
Again, this is a decimal value. In hexadecimal, this is 0x3390.
The lower order byte for Group 1, 0x90, is loaded into register 0x62. The higher-order byte, 0x33, is loaded into
the 7 least-significant bits of register 0x63. As with the Group 0 settings, bit 7 of register 0x63 is also set.
When this is complete, register 0x62 will contain 0x90. Register 0x63 will contain 0xb3.
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