DS125DF410_13 Datasheet, PDF (25/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
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Address (Hex)
0x29
0x2a
0x2c
0x2d
0x2f
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x39
0x3a
0x3e
0x40 – 0x5f
SNLS398E – JANUARY 2012 – REVISED MAY 2013
Table 7. Channel Registers (continued)
Bits
Default Value (Hex) Mode
6:5
0x0
R
7:0
0x30
R/W
5:4
0x3
R/W
3:0
0x2
R/W
2:0
0x0
R/W
7:6
0x0
R/W
5:4
0x0
R/W
3
0x0
R/W
2
0x1
R/W
1
0x1
R/W
0
0x0
R/W
4
0x0
R
3
0x0
R/W
1:0
0x0
R/W
6:5
0x1
R/W
4:3
0x0
R/W
7:4
0x1
R/W
3:0
0x1
R/W
7:4
0x8
R/W
3:0
0x8
R/W
3:0
0xf
R/W
4:0
0x1f
R/W
6
0x0
R/W
5:4
0x3
R/W
2
0x0
R/W
1:0
0x1
R/W
4:0
0x0
R/W
7:6
0x2
R/W
5:4
0x2
R/W
3:2
0x1
R/W
1:0
0x1
R/W
7
0x1
R/W
CTLE Settings for Adaptation – see Table 14
Field Name
Description
eom_vrange_setting[1: Eye Opening Monitor Voltage Range
0]
Setting <1:0>
eom_timer_thr[7:0]
Eye Opening Monitor Timer Threshold
<7:0>
dfe_sm_fom[1:0]
DFE Adaptation Figure of Merit Type <1:0>
dfe_adapt_counter[3:0] Counter Used in Adaptation for Look-
Beyond when Figure of Merit Decreases
drv_sel_vod[2:0]
Driver VOD <2:0>
RATE[1:0]
Rate <1:0>
SUBRATE[1:0]
Subrate <1:0>
index_ov
CTLE Adaptation Index Override (Register
0x13)
en_ppm_check
Enable Frequency Counter for Lock Detect
en_fld_check
False Lock Detector for lock detect is
disabled by default. Must set bit to 0 to
enable the FLD.
ctle_adapt
Start CTLE Adaptation
heo_veo_interrupt
Goes High if Interrupt from CDR Goes High
prbs_en_dig_clk
PRBS Generator Enable
prbs_pattern_sel[1:0] PRBS Generator Pattern Select <1:0>
adapt_mode[1:0]
Adaptation Mode <1:0>
eq_sm_fom[1:0]
CTLE Adaptation Figure of Merit Type
<1:0>
heo_int_thresh[3:0]
HEO Interrupt Threshold <3:0>
veo_int_thresh[3:0]
VEO Interrupt Threshold <3:0>
heo_thresh[3:0]
HEO Threshold for CTLE Adaptation
Handoff to DFE Adaptation <3:0>
veo_thresh[3:0]
VEO Threshold for CTLE Adaptation
Handoff to DFE Adaptation <3:0>
dfe_max_tap_2_5[3:0] Maximum DFE Tap Absolute Value for
Taps 2–5 <3:0>
dfe_max_tap_1[4:0]
Maximum DFE Tap Absolute Value for Tap
1 <4:0>
heo_veo_int_enable Enable HEO/VEO Interrupt
ref_mode[1:0]
Reference Clock Mode <1:0>
mr_cdr_cap_dac_rng_o Enable Override for VCO Cap DAC Range
v
mr_cdr_cap_dac_rng[1: Cap DAC Range <1:0>
0]
start_index[4:0]
Start Index for CTLE Adaptation <4:0>
(Enable from Register 0x2f, Bit 3)
fixed_eq_BST0[1:0]
Fixed CTLE Stage 0 Boost Setting for
Lower Data Rates <1:0>
fixed_eq_BST1[1:0]
Fixed CTLE Stage 1 Boost Setting for
Lower Data Rates <1:0>
fixed_eq_BST2[1:0]
Fixed CTLE Stage 2 Boost Setting for
Lower Data Rates <1:0>
fixed_eq_BST3[1:0]
Fixed CTLE Stage 3 Boost Setting for
Lower Data Rates <1:0>
HEO_VEO_LOCKMON Enable HEO/VEO Lock Monitoring
_EN
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