DS125DF410_13 Datasheet, PDF (24/44 Pages) Texas Instruments – DS125DF410 Low Power Multi-Rate Quad Channel Retimer

DS125DF410
SNLS398E – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Address (Hex) Bits
0x09
7
5
2
0x0a
3
2
0x0b
4:0
0x0d
5
0x11
7:6
5
3
2
1
0
0x12
7
4:0
0x13
2
0x14
7
6
0x15
7
6
2:0
0x18
6:4
2
0x1e
7:5
4
3
0x1f
7
0x20
7:4
3:0
0x21
7:4
3:0
0x23
6
0x24
7
2
0
0x25
7:0
0x26
7:0
0x27
7:0
0x28
7:0
Table 7. Channel Registers (continued)
Default Value (Hex) Mode
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0f
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x00
R/W
0x0
RW
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x4
R/W
0x0
R/W
0x7
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W/SC
0x0
R/W/SC
0x0
R
0x0
R
0x0
R
0x0
R
Field Name
Description
reg_divsel_vco_cap_ov Enable Override VCO Cap DAC (Registers
0x08 and 0x0b)
reg_bypass_pfd_ov
Enable Override Output Mux (Register
0x1e)
reg_divsel_ov
Enable Override Divider Select (Register
0x18)
reg_cdr_reset_ov
Enable CDR Reset Override (Register
0x0a)
reg_cdr_reset_sm
CDR Reset Override Bit
cdr_cap_dac_start1[4:0 Override VCO Cap DAC Setting 1 <4:0>
]
PRBS_PATT_SHIFT_E PRBS Generator Clock Enable
N
eom_sel_vrange[1:0] Eye Opening Monitor Voltage Range <1:0>
eom_PD
Eye Opening Monitor Power Down
dfe_tap2_pol
DFE Tap 2 Polarity
dfe_tap3_pol
DFE Tap 3 Polarity
dfe_tap4_pol
DFE Tap 4 Polarity
dfe_tap5_pol
DFE Tap 5 Polarity
dfe_tap1_pol
DFE Tap 1 Polarity
dfe_wt1[4:0]
DFE Tap 1 Weight <4:0>
eq_BST3[2]
CTLE Boost Stage 3, Bit 2 (Limiting Bit)
eq_sd_preset
Force Signal Detect On
eq_sd_reset
Force Signal Detect Off
dfe_manual_tap_en Enables manual DFE tap settings
drv_dem_range
Driver De-emphasis Range
drv_dem[2:0]
Driver De-emphasis Setting<2:0>
pdiq_sel_div[2:0]
VCO Divider Ratio <2:0> (Enable from
Register 0x09, Bit 2)
drv_sel_slow
Enable Slow Rise/Fall Time on Output
Driver
pfd_sel_data_mux[2:0] OutputMux <2:0> (Enable from Register
0x09, Bit 5)
prbs_en
Enable PRBS Generator
dfe_PD
DFE is powered down by default. Must set
bit to 0 to power up the DFE.
drv_sel_inv
Select Output Polarity Inverted
dfe_wt5[3:0]
DFE Tap 5 Weight <3:0>
dfe_wt4[3:0]
DFE Tap 4 Weight <3:0>
dfe_wt3[3:0]
DFE Tap 3 Weight <3:0>
dfe_wt2[3:0]
DFE Tap 2 Weight <3:0>
dfe_ov
DFE Override
fast_eom
Enable Fast Eye Opening Monitor Mode
dfe_adapt
Start DFE Adaptation (Self-Clearing)
eom_start
Start Eye Opening Monitor Counter (Self-
Clearing)
eom_count[15:8]
Eye Opening Monitor Count <15:8>
eom_count[7:0]
Eye Opening Monitor Count <7:0>
heo[7:0]
HEO Value <7:0>
veo[7:0]
VEO Value <7:0>
24
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