TL16C550B Datasheet, PDF (6/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
Terminal Functions (Continued)
TERMINAL
NAME
NO. NO. NO. ^I/O
N FN PT
DESCRIPTION
RD1
RD2
21 24 19
22 25 20
I Read inputs. When either input is active (low or high respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation; the other input should be tied in its inactive state
(i.e., RD2 tied low or RD1 tied high).
RI
39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input has
transitioned from a low to a high state since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.
RTS
32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive
(high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
of the MCR.
RXRDY
29 32 29 O Receiver ready output. Receiver direct memory access (DMA) signalling is available with this terminal.
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed.
Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1
supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO
has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one
character in the receiver FIFO or receiver holding register, RXRDY is active low. When RXRDY has
been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high).
In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY
goes active (low); when it has been active but there are no more characters in the FIFO or holding
register, it goes inactive (high).
SIN
10 11 7 I Serial data input. Input from a connected communications device
SOUT
11 13 8 O Composite serial data output. Output to a connected communication device. SOUT is set to the marking
(set) state as a result of master reset.
TXRDY
24 27 23 O Transmitter ready output. Transmitter DMA signalling is available with this terminal. When operating in
the FIFO mode, one of two types of DMA signalling can be selected using FCR3. When operating in
the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.
VCC
VSS
WR1
WR2
40 44 42
20 22 18
18 20 16
19 21 17
5-V supply voltage
Supply common
I Write inputs. When either input is active (high or low respectively) and while the ACE is selected, the
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is
required to transfer data during a write operation; the other input should be tied in its inactive state (i.e.,
WR2 tied low or WR1 tied high).
XIN
XOUT
16 18 14 I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
17 19 15
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