TL16C550B Datasheet, PDF (20/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB† A2
A1
A0
REGISTER
0
L
L
L Receiver buffer (read), transmitter holding (write)
0
L
L
H Interrupt enable register
X
L
H
L Interrupt identification register (read only)
X
L
H
L FIFO control register (write)
X
L
H
H Line control register
X
H
L
L Modem control register
X
H
L
H Line status register
X
H
H
L Modem status register
X
H
H
H Scratch register
1
L
L
L Divisor latch (LSB)
1
L
L
H Divisor latch (MSB)
† _{The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal}
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2
RTS
DTR
OUT1
Scratch Register
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Registers
RCVR FIFO
XMIT FIFO
RESET
CONTROL
RESET STATE
Master Reset
All bits cleared (bits 0 – 3 forced and bits 4 – 7 permanent)
Master Reset
Bit 0 is set, bits 1 – 3 are cleared, and bits 4 – 7 are permanently
cleared
Master Reset
All bits cleared
Master Reset
All bits cleared
Master Reset
All bits cleared (5 – 7 permanent)
Master Reset
Bits 5 and 6 are set, all other bits are cleared
Master Reset
Bits 0 – 3 are cleared, bits 4 – 7 are input signals
Master Reset
Read LSR/MR
Read RBR/MR
High
Low
Low
Read IR/Write THR/MR Low
Read MSR/MR
Low
Master Reset
High
Master Reset
High
Master Reset
High
Master Reset
High
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
MR/FCR1 – FCR0/
∆FCR0
All bits low
MR/FCR2 – FCR0/
∆FCR0
All bits low
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