TL16C550B Datasheet, PDF (21/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
0 DLAB = 0 0 DLAB = 0
Receiver Transmitter
Bit
Buffer
No.
Register
(Read
Holding
Register
(Write
Only)
Only)
RBR
THR
0 Data Bit 0† Data Bit 0
1
Data Bit 1
Data Bit 1
2
Data Bit 2
Data Bit 2
3
Data Bit 3
Data Bit 3
4
Data Bit 4
Data Bit 4
1 DLAB = 0
Interrupt
Enable
Register
IER
Enable
Received
Data
Available
Interrupt
(ERBI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Enable
Modem
Status
Interrupt
(EDSSI)
0
2
Interrupt
Ident.
Register
(Read
Only)
IIR
0 if
interrupt
Pending
Interrupt
ID
Bit (1)
Interrupt
ID
Bit (2)
Interrupt
ID
Bit (2)
(see
Note 4)
0
2
FIFO
Control
Register
(Write
Only)
FCR
FIFO
Enable
REGISTER ADDRESS
3
4
Line
Control
Register
Modem
Control
Register
LCR
Word
Length
Select
Bit 0
(WLS0)
MCR
Data
Terminal
Ready
(DTR)
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
DMA
Mode
Select
Parity
Enable
(PEN)
Reserved
Even
Parity
Select
(EPS)
OUT2
Loop
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
0
Parity
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(LSB)
Break
Control
0
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
0
(DLAB)
† _{Bit 0 is the least significant bit. It is the first bit serially transmitted or received.}
NOTE 4: These bits are always 0 in the TL16C450 mode.
5
Line
Status
Register
LSR
Data
Ready
(DR)
6
7
0 DLAB = 1
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
MSR
SCR
DLL
Delta
Clear
to Send
Bit 0
Bit 0
(∆CTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(∆DSR)
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Framing
Error
(FE)
Break
Interrupt
(BI)
Transmitter
Holding
Register
(THRE)
Transmitter
Empty
(TEMT)
Error in
RCVR
FIFO
(see
Note 4)
Delta
Data
Carrier
Detect
(∆DCD)
Clear
to
Send
(CTS)
Data
Set
Ready
(DSR)
Ring
Indicator
(RI)
Data
Carrier
Detect
(DCD)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1 DLAB = 1
Latch
(MSB)
DLM
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
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