TL16C550B Datasheet, PDF (24/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT output signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table3 and are described in the following bulleted list.
D Bit 0: This bit when set enables the received data available interrupt.
D Bit 1: This bit when set enables the THRE interrupt.
D Bit 2: This bit when set enables the receiver line status interrupt.
D Bit 3: This bit when set enables the modem status interrupt.
D Bits 4 – 7: These bits in the IER are not used and are always cleared.
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors. The ACE provides four prioritized levels of interrupts which are:
D Priority 1 – Receiver line status (highest priority)
D Priority 2 – Receiver data ready or receiver character timeout
D Priority 3 – Transmitter holding register empty
D Priority 4 – Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of that interrupt in its
three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described
in Table 4. Detail on each bit are as follows:
D Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
D Bits 1 and 2: These two bits identify the highest priority interrupt pending, as indicated in Table 5.
D Bit 3. This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a timeout interrupt is pending.
D Bits 4 – 5: These two bits are not used and are always cleared.
D Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FIFO
control register is set.
24
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265