TL16C550B Datasheet, PDF (23/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupt occurs as follows:
1. FIFO timeout interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received is longer than four continuous character times ago (when
two stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO is longer than four continuous character times
ago. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer is reset when the microprocessor
reads one character from the receiver FIFO.
4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:
1. The transmitter holding register interrupt (02) occurs when the transmit FIFO is empty. It is cleared as
soon as the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this
interrupt) or the IIR is read.
2. The transmit FIFO empty indications are delayed one character time minus the last stop bit time when
the following occurs: THRE = 1 and there have not been at least two bytes at the same time in the
transmit FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate
when it is enabled.
Character timeout and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt.
FIFO polled mode operation
When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled
mode of operation.
In this mode, the user program checks receiver and transmitter status via the LSR. As stated previously:
• LSR0 is set as long as there is one byte in the receiver FIFO.
• LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the transmit FIFO is empty.
• LSR6 indicates that both the transmit FIFO and shift registers are empty.
• LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO polled mode. However, the receiver
and transmit FIFOs are still fully capable of holding characters.
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