TL16C550B Datasheet, PDF (22/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
Bit 0: FCR0, when set, enables the transmit and receive FIFOs. This bit must be set when other FCR bits are
written to or they are not programmed. Changing this bit clears the FIFOs.
D Bit 1: FCR1, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.
D Bit 2: FCR2, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.
D Bit 3: When FCR0 is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to
mode 1.
D Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT 7
0
0
1
1
BIT 6
0
1
0
1
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1) receiver interrupt occur as
follows:
1. The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 0110) has higher priority than the received data available
interrupt (IIR = 0100).
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver
FIFO. It is cleared when the FIFO is empty.
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