TL16C550B Datasheet, PDF (29/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
D Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCRs bit 2 (OUT1).
D Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
bit 7 is equivalent to the MCRs bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
and divides it by a divisor in the range between 1 and (2¹⁶ –1). The output frequency of the baud generator is
16 × the baud rate. The formula for the divisor is:
divisor # = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 8 and 9 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbit/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency. Refer to Figure 16 for examples of typical
clock circuits.
Table 8. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
DIVISOR USED
TO GENERATE
16 × CLOCK
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
0.026
0.058
0.69
2.86
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