TL16C550B Datasheet, PDF (14/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
SIN
Data Bits 5 – 8
Stop
Sample Clock
Trigger-Level
Interrupt
(FCR6, 7 = 0, 0)
INTRPT
Line Status
Interrupt (LSI)
RD1
(RD LSR)
td13
(see Note A)
50%
50%
50%
td14
50%
td14
Active
50%
RD1
(RD RBR)
Active
50%
NOTE A: For a timeout interrupt, td13 = 8 RCLKs.
Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms
(FIFO at or above
trigger level)
(FIFO below
trigger level)
SIN
Sample Clock
Timeout or
Trigger-Level
Interrupt
Line Status
Interrupt (LSI)
RD1, RD2
(RDLSR)
Stop
td13
(see Note A)
50%
50%
td14
Top Byte of FIFO
50%
td13
td14
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RD1, RD2
(RDRBR)
Active 50%
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, td13 = 8 RCLKs.
50%
Active
Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
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