TL16C550B Datasheet, PDF (28/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
D Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
D Bit 4: This bit provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
– The SOUT is set high.
– The SIN is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to their inactive (high) states.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt’s sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
D Bits 5 – 7: These bits are permanently cleared.
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
D Bit 0: This bit is the change in clear-to-send (∆ CTS) indicator. Bit 0 indicates that the CTS input has
changed states since the last time it was read by the CPU . When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
D Bit 1: This bit is the change in data set ready (∆ DSR) indicator. Bit 1 indicates that the DSR input has
changed states since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
D Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. Bit 2 indicates that the RI input to the
chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled,
a modem status interrupt is generated.
D Bit 3: This bit is the change in data carrier detect (∆ DCD) indicator. Bit 3 indicates that the DCD input to
the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
D Bit 4: This bit is the complement of the clear-to-send (CTS) input. When bit 4 (loop) of the MCR is set,
bit 4 is equivalent to the MCR bit 1 (RTS).
D Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
bit 5 is equivalent to the MCR bit 1 (DTR).
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