TL16C550B Datasheet, PDF (27/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
line status register (LSR) (continued)^†
D Bit 2^‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.
D Bit 3^‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.
D Bit 4^‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held cleared for longer than a full-word transmission time. A full-word transmission time is defined as
the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.
D Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
D Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.
D Bit 7: In the TL16C550B and the TL16C550BI mode, this bit is always cleared. In the TL16C450 mode, this
bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error
in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in
the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
D Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its low state. When bit 0 is cleared, DTR goes high.
D Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over
the DTR output.
D Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.}
‡ _{Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.}
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