SMJ320C6701_07 Datasheet, PDF (57/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
DR
1
2
7
6
Bit 0
Bit 0
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 36)
’C6701-14
’C6701-16
NO.
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low
12
2 – 3P
ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low
4
5 + 6P
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
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