SMJ320C6701_07 Datasheet, PDF (24/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
documentation support (continued)
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of
devices.
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation,
application programming interfaces, and technical reference material.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools
and APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides
access to information pertaining to the SMJ320 family, including documentation, source code, and object code
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise
and fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency =
20-30 MHz, maximum dB attenuation = 45-50 dB, and minimum dB attenuation above 30 MHz = 20 dB.
Table 3. CLKOUT1 Frequency Ranges^†
PLLFREQ3
(C13)
PLLFREQ2
(G11)
PLLFREQ1
(F11)
CLKOUT1 Frequency Range
(MHz)
0
0
0
50–140
0
0
1
65–167
0
1
0
130–167
† _{Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain}
the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example,
for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value
of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
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