SMJ320C6701_07 Datasheet, PDF (45/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
EXTERNAL INTERRUPT/RESET TIMING
timing requirements for interrupt response cycles^†‡ (see Figure 26)
’C6701-14
NO.
’C6701-16
UNIT
MIN MAX
2 tw(ILOW)
Width of the interrupt pulse low
*2P
ns
3 tw(IHIGH)
Width of the interrupt pulse high
*2P
ns
† _{Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can}
be connected to asynchronous inputs.
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.}
*This parameter is not tested.
switching characteristics during interrupt response cycles^§ (see Figure 26)
NO.
PARAMETER
1 tR(EINTH-IACKH) Response time, EXT_INTx high to IACK high
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.}
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
’C6701-14
’C6701-16
MIN MAX
9P
–0.5P 13 – 0.5P
10 – 0.5P
–0.5P
1
UNIT
ns
ns
ns
ns
CLKOUT2
2
EXT_INTx, NMI
Intr Flag
IACK
INUMx
3
4
4
6
5
Interrupt Number
Figure 26. Interrupt Timing
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