SMJ320C6701_07 Datasheet, PDF (31/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2^† (see Figure 10)
NO.
PARAMETER
1 tc(CKO2)
Cycle time, CLKOUT2
2 tw(CKO2H) Pulse duration, CLKOUT2 high
3 tw(CKO2L)
Pulse duration, CLKOUT2 low
4 tt(CKO2)
Transition time, CLKOUT2
† _{P = 1/CPU clock frequency in ns.}
*This parameter is not tested.
’C6701-14
’C6701-16
MIN
MAX
*2P – 0.7 *2P + 0.7
*P – 0.7 *P + 0.7
*P – 0.7 *P + 0.7
*0.6
UNIT
ns
ns
ns
ns
CLKOUT2
1
4
2
3
4
Figure 10. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
PARAMETER
1 td(CKO1-SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
2 td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
3 td(CKO1-CKO2)
Delay time, CLKOUT1 edge to CLKOUT2 edge
4 td(CKO1-SDCLK)
Delay time, CLKOUT1 edge to SDCLK edge
’C6701-14
’C6701-16
MIN MAX
–0.8 3.4
–1.0 3.0
–1.5 2.5
–1.5 1.9
UNIT
ns
ns
ns
ns
CLKOUT1
1
SSCLK
2
SSCLK (1/2rate)
3
CLKOUT2
4
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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