SMJ320C6701_07 Datasheet, PDF (43/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
RESET TIMING
SGUS030B – APRIL 2000 – REVISED MAY 2001
timing requirements for reset (see Figure 25)
’C6701-14
NO.
’C6701-16
UNIT
MIN MAX
1 tw(RESET)
Width of the RESET pulse (PLL stable)^†
Width of the RESET pulse (PLL needs to sync up)^‡
*10
*250
CLKOUT1
cycles
µs
† _{This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.}
*This parameter is not tested.
‡ _{This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may}
need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the clock PLL section for PLL lock times.
switching characteristics during reset^§ (see Figure 25)
NO.
PARAMETER
’C6701-14
’C6701-16
MIN MAX
UNIT
2 tR(RESET)
Response time to change of value in RESET signal
*1
CLKOUT1
cycles
3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid
*–1
ns
4 td(CKO1H-CKO2V)
Delay time, CLKOUT1 high to CLKOUT2 valid
*10
ns
5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid
*–1
ns
6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid
*10
ns
7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid
*–1
ns
8 td(CKO1H-SSCKV)
Delay time, CLKOUT1 high to SSCLK valid
*10
ns
9 td(CKO1H-LOWIV)
Delay time, CLKOUT1 high to low group invalid
*–1
ns
10 td(CKO1H-LOWV)
Delay time, CLKOUT1 high to low group valid
*10
ns
11 td(CKO1H-HIGHIV)
Delay time, CLKOUT1 high to high group invalid
*–1
ns
12 td(CKO1H-HIGHV)
Delay time, CLKOUT1 high to high group valid
*10
ns
13 td(CKO1H-ZHZ)
Delay time, CLKOUT1 high to Z group high impedance
*–1
ns
14 td(CKO1H-ZV)
Delay time, CLKOUT1 high to Z group valid
*10
ns
§ _{Low group consists of:}
High group consists of:
Z group consists of:
*This parameter is not tested.
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
HRDY and HINT.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
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