SMJ320C6701_07 Datasheet, PDF (36/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)
NO.
7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high
8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high
’C6701-14
MIN MAX
3.8
1.5
’C6701-16
MIN MAX
3.8
1.5
UNIT
ns
ns
switching characteristics for synchronous-burst SRAM cycles^† (half-rate SSCLK)
(see Figure 16 and Figure 17)
NO.
PARAMETER
’C6701-14
MIN
MAX
’C6701-16
UNIT
MIN
MAX
1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high
1.5P – 5.5
1.5P – 4.5
ns
2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high
1.5P – 5.5
1.5P – 4.5
ns
4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high
1.5P – 5.5
1.5P – 4.5
ns
6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P – 5.5
1.5P – 4.5
ns
10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high
1.5P – 5.5
1.5P – 4.5
ns
12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high
1.5P – 5.5
1.5P – 4.5
ns
14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high
0.5P – 2.3
0.5P – 2.2
ns
15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 5.5
1.5P – 4.5
ns
16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high
0.5P – 2.3
0.5P – 2
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.}
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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