SMJ320C6701_07 Datasheet, PDF (38/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 18)
NO.
7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high
8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high
’C6701-14
MIN MAX
2
3
’C6701-16
MIN MAX
2
3
UNIT
ns
ns
switching characteristics for synchronous DRAM cycles^† (see Figure 18–Figure 23)
NO.
PARAMETER
’C6701-14
MIN
MAX
’C6701-16
UNIT
MIN
MAX
1 tosu(CEV-SDCLKH)
Output setup time, CEx valid before SDCLK high
1.5P – 5
1.5P – 4
ns
2 toh(SDCLKH-CEV)
Output hold time, CEx valid after SDCLK high
0.5P – 1.9
0.5P – 1.5
ns
3 tosu(BEV-SDCLKH)
Output setup time, BEx valid before SDCLK high
1.5P – 5
1.5P – 4
ns
4 toh(SDCLKH-BEIV)
Output hold time, BEx invalid after SDCLK high
0.5P – 1.9
0.5P – 1.5
ns
5 tosu(EAV-SDCLKH)
Output setup time, EAx valid before SDCLK high
1.5P – 5
1.5P – 4
ns
6 toh(SDCLKH-EAIV)
Output hold time, EAx invalid after SDCLK high
0.5P – 1.9
0.5P – 1.5
ns
9
tosu(SDCAS-SDCLKH)
Output setup time, SDCAS valid before SDCLK
high
1.5P – 5
1.5P – 4
ns
10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P – 1.9
0.5P – 1.5
ns
11 tosu(EDV-SDCLKH)
Output setup time, EDx valid before SDCLK high
1.5P – 5
1.5P – 4
ns
12 toh(SDCLKH-EDIV)
Output hold time, EDx invalid after SDCLK high
0.5P – 1.9
0.5P – 1.5
ns
13 tosu(SDWE-SDCLKH)
Output setup time, SDWE valid before SDCLK
high
1.5P – 5
1.5P – 4
ns
14 toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high 0.5P – 1.9
0.5P – 1.5
ns
15
tosu(SDA10V-SDCLKH)
Output setup time, SDA10 valid before SDCLK
high
1.5P – 5
1.5P – 4
ns
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK
high
0.5P – 1.9
0.5P – 1.5
ns
Output setup time, SDRAS valid before SDCLK
17 tosu(SDRAS-SDCLKH) _high
1.5P – 5
1.5P – 4
ns
18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 1.9
0.5P – 1.5
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.}
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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